In a package such as a flip chip Chip Scale Package (fcCSP), an integrated circuit (IC) may be mounted to a substrate (e.g., a printed circuit board (PCB) or other integrated circuit carrier) through a bump on trace (BOT) interconnection.
In light of the demand for ever smaller packages, attempts are often made to reduce the distance between adjacent bumps, which is known as the bump pitch. One way to reduce the bump pitch is by shrinking the width of the metal traces used in the BOT interconnection. Unfortunately, reducing the width of the metal traces may lead to undesirable or detrimental consequences.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.